This group includes the instructions for conditional and unconditional jump, subroutine call and return, and restart. The DAA instruction operates on this result and gives the final result in the decimal system.
It uses carry and auxiliary carry for decimal adjustment. Similarly, 6 is also added to 4 MSBs of the content of the accumulator if their value lies in between A and F or the CS flag is set to 1.
All status flags are affected. When DAA is used data should be in decimal numbers. The 2nd byte of the instruction is data, and it is subtracted from the content of the accumulator. The status flags are set according to the result of subtraction. But the result is discarded. The content of the accumulator remains unchanged. The content of the accumulator is rotated left by one bit.
The seventh bit of the accumulator is moved to carry bit as well as to the zero bit of the accumulator. Only CS flag is affected. The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to the seventh bit as well as to carry bit.
CALL instruction is used to call a subroutine. Before the control is transferred to the subroutine, the address of the next instruction of the main program is saved in the stack. The content of the stack pointer is decremented by two to indicate the new stack top. Then the program jumps to subroutine starting at address specified by the label. Search Search.
Arithmetic Group The instructions of this group perform arithmetic operations such as addition, subtraction; increment or decrement of the content of a register or memory. Branch Control Group This group includes the instructions for conditional and unconditional jump, subroutine call and return, and restart.
Move the content of register to memory. Move immediate data to register. MVI M, data. Khaled A. Microprocessors Monday, Apr. INT- interrupt program execution 1. It decrements the sp by 2 and pushes the flag registers on the stack. Decrement the sp by 2 and push the content.
Similar presentations. Upload Log in. My presentations Profile Feedback Log out. Log in. CBW : Convert signed byte or word This instruction converts a signed byte to a signed word i. CBW does not affect any flags. Using bit-7 of AL is moved to all the bits of AH register.
CWD is used for sign extension of bit number into bit number. CWD does not affect any flags. Bit of AX is moved to all the bits of DX register. Thus performing logical operation on two memory bytes or words simultaneously is not possible.
The destination can be a register or a memory location specified by any one of the addressing mode except for immediate addressing mode. No flags are affected by the NOT instruction. The result is stored in destination operand. At least one of the operands should be a register or an memory location , but both the operands cannot be memory locations or immediate operands and also immediate operand cannot be a destination operand.
The AND operation gives output 1 only when both the inputs are high. At least one of the operands should be a register or an memory location, but both the operands cannot be memory locations or immediate operands and also immediate operand cannot be a destination operand. The OR operation gives output 1 when any one of the inputs are high.
The XOR operation gives output 1 only when both the inputs are dissimilar. The source and destination operands are not altered they simply update the flags. The result of the ANDing operation is not available for further use,but flags are affected. The TEST instruction is often used to set flags before a conditional jump instruction. The source operand can be a register or a memory location or immediate data.
The destination operand can be either a register or a memory location. But both source and destination cannot be memory location. The number of bits to be shifted if 1 will be specified in the instruction itself if the count is more than 1 then the count will be in CL register. The operand to be shifted can be either register or memory location contents but cannot be immediate data. All the flags are affected depending upon the result. The shift operation will considering using carry flag.
The result of the shift operation will be stored in the register itself. SAR instruction inserts the most significant bit of the operand in the newly inserted bit positions. The remaining bits are shifted left subsequently by the specified count positions. The operand can be a register or a memory location.
The count will be in instruction if it is 1, and in CL register if greater than 1. RCL : Rotate left through i. The remaining bits are shifted right subsequently by the specified count positions. RCR : Rotate right through i. The pointers are updated i. On the other hand, if it is a wordstring operation,the indexregistersareupdatedby two. The counteris decremented by one for both byte and word strings. Prefix instructions 2. When CX becomes zero , the execution proceeds to the next instruction in the sequence.
The SI register points to the source string and DI register points to the destination string. The DI register points to the string byte or word.
The DI register is automatically incremented or decremented depending on the status of DF. The SI register points to the source string. The SI register is automatically incremented or decremented depending on the status of DF. The DI register points to the destination string.
These instructions control the functioning of the available hardware programmer accessible hardware inside the processor chip. If a valid interrupt signal occurs while the is in idle state, the will return to the idle state afterthe interrupt serviceprocedureexecutes. It returnsto the idle state because the address of the WAIT instruction is the address pushed on to the stack when the responds to the interrupt request.
The will enter a halt state i. NOP : No Operation No operation is performed for three clock periods This instruction simply uses up three clock cycles and increments the instruction pointer to point to the next instruction. The NOP instruction does not affect any flag. The NOP instruction can be used to increase the delay of a delay loop.
Whenhand coding, a NOP can also be usedto hold aplace in a programforinstruction that will be added later. This instruction is used to pass instructions to a coprocessor , such as the math coprocessor which shares the address and data bus with Instructions for coprocessor are represented by a 6-bit code embedded in the escape instruction. As fetches the instructions bytes, the coprocessor also catches these bytes from the data bus and puts them in its queue , but treats all the normal instructions as NOPs and when ESC instruction is fetched by , the coprocessor decodesthe instruction and carries out the action specified by the 6-bit code in the instruction.
In most cases treats the ESC instruction as NOP but in some cases will access a data item in memory for the coprocessor. For ESC opcode, Mem format the data is accessed by from memory For ESC opcode, Mem format the data is accessed by from register specified in the instruction. When LOCK prefix is used in an instruction then during execution of this instruction the lock prefix ensures that the shared system resources are not taken over by other bus masters in the middle of the critical instruction execution.
When an instruction with LOCK prefix is executed the will assert its bus lock signal output. The ALU uses 4 bits for control. Out of the 16 possible combinations, only 6 are used for the subset under consideration.
This is indicated in Figure 9. Depending on the type of instruction class, the ALU will need to perform one of the first five functions. For the load word and store word instructions, we use the ALU to compute the memory address. This is done by addition. For the R-type instructions, the ALU needs to perform one of the five actions AND, OR, subtract, add, or set on less than , depending on the value of the 6-bit funct or function field in the low-order bits of the instruction refer to the instruction formats.
For a branch on equal instruction, the ALU must perform a subtraction, for comparison. We can generate the 4-bit ALU control input using a small control unit that takes as inputs the function field of the instruction and a 2-bit control field, which we call ALUOp.
ALUOp indicates whether the operation to be performed should be add 00 for loads and stores, subtract 01 for beq, or determined by the operation encoded in the funct field The output of the ALU control unit is a 4-bit signal that directly controls the ALU by generating one of the 4-bit combinations shown previously.
In Figure 9. The opcode, listed in the first column, determines the setting of the ALUOp bits. For completeness, the relationship between the ALUOp bits and the instruction opcode is also shown.
Later on we will see how the ALUOp bits are generated from the main control unit. This style of using multiple levels of decoding—that is, the main control unit generates the ALUOp bits, which then are used as input to the ALU control that generates the actual signals to control the ALU unit—is a common implementation technique.
Using multiple levels of control can reduce the size of the main control unit. Using several smaller control units may also potentially increase the speed of the control unit.
Such optimizations are important, since the control unit is often performance-critical. There are several different ways to implement the mapping from the 2-bit ALUOp field and the 6-bit funct field to the three ALU operation control bits. Because only a small number of the 64 possible values of the function field are of interest and the function field is used only when the ALUOp bits equal 10, we can use a small piece of logic that recognizes the subset of possible values and causes the correct setting of the ALU control bits.
Now, we shall consider the design of the main control unit. All these details are indicated in Figure 9. To the simple datapath already shown, we shall add all the required control signals. Since all the multiplexors have two inputs, they each require a single control line. There are seven single-bit control lines plus the 2-bit ALUOp control signal. The seven control signals are listed below:. RegDst: The control signal to decide the destination register for the register write operation — The register in the Rt field or Rd field.
MemtoReg: The control signal which decides what is written into the register file, the result of the ALU operation or the data memory contents. The datapath along with the control signals included is shown in Figure 9. Note that the control unit takes in the opcode information from the fetched instruction and generates all the control signals, depending on the operation to be performed. Now, we shall trace the execution flow for different types of instructions and see what control signals have to be activated.
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